The present invention relates to a semiconductor device and a fabrication method thereof, and particularly to a semiconductor device in which an n-channel field effect transistor and a p-channel field effect transistor are provided on a common base-substrate, and a fabrication method thereof.
In recent years, along with rapid advance in digitization of information processing means, there have been strong demands to increase the operational speeds of semiconductor devices and to reduce the power consumption of semiconductor devices. Conventionally, the increase in operational speed of semiconductor devices has been achieved by making finer device structures, and the reduction in power consumption thereof has been achieved by adopting semiconductor devices of a complementary type including n-channel and p-channel field effect transistors. The technique for making finer device structures, however, has already reached a limitation of a lithography process, in which a pattern having a size smaller than a wavelength of exposure light has been needed to be formed by lithography, and accordingly, at the lithography step, it has come to be difficult to ensure a sufficient process tolerance. In other words, the attempt to increase the operational speeds of semiconductor devices by making finer device structures is coming closer to a limitation.
For field effect transistors, there has been proposed an attempt to solve the above problem by imparting a strain effect to a channel layer. The formation of devices using a material layer having such a strain effect has become possible by an advanced thin film formation technology using a group IV element containing semiconductor material such as silicon or a silicon-germanium compound, and at present, improved low voltage devices have been actively developed by using material layers having the strain effect.
The strain effect means a phenomenon that if stress is applied to a semiconductor thin film, the energy band of the semiconductor is strained, to thereby change the effective masses of carriers in the semiconductor. The formation of a semiconductor thin film having the strain effect has become possible by controlling an internal stress applied to a multi-layer film typically containing a silicon layer and a silicon-germanium compound layer by a molecular beam epitaxy process or an ultrahigh vacuum chemical vapor deposition process (UHV-CVD). High performance MOS based devices, sensors, and the like of a type in which a difference in band gap and film strain are controlled by hetero-junction have been also developed.
A silicon based MOS (Metal-Oxide-Semiconductor) including layers each having a strain effect can be produced by sequentially stacking a buffer layer made from a silicon-germanium compound having a germanium concentration gradually increased toward an upper surface of the buffer layer, a relax layer made from a silicon-germanium compound, and a silicon layer on a silicon substrate in this order. In this MOS transistor, since tensile stress is generated in the silicon layer, a strain effect due to the tensile stress appears, with a result that the mobility of electrons is increased by the strain effect in the silicon layer; and since compressive stress is generated in the silicon-germanium compound layer formed on the silicon substrate, a strain effect due to the compressive stress appears, with a result that the mobility of positive holes is increased by the strain effect in the silicon-germanium compound layer.
A field effect transistor produced by controlling stress in a channel layer by making use of the above-described strain effect exhibits a high mutual conductance [gm (mobility)]. A pMOS transistor produced by making use of the strain effect has been disclosed in Appl. Phys. Letter (USA), 63(1993) S. P. Voinigensen et al., p660, and IEEE Electronic Devices (USA), 43(1996), L. H. Jiang and R. G. Elliman, p97. Further, an nMOS transistor produced by making use of the strain effect has been disclosed in Appl. Phys. Letter (USA), 64(1994) K. Ismail et al., p3124 and IEDM 94-37 (USA), (1994) J. Welser et al.
The semiconductor devices produced by making use of the strain effect have the following problem:
In a silicon layer formed on a relax layer, the mobility of electrons is increased by the strain effect due to tensile stress; however, the mobility of positive holes is reduced. Accordingly, while an nMOS transistor having an improved low voltage can be obtained, the performance of a pMOS transistor cannot be improved, with a result that the performance of the CMOS cannot be significantly improved.
On the other hand, in a silicon-germanium compound layer formed on a silicon substrate, the mobility of positive holes is improved by the strain effect due to compressive stress; however, the mobility of electrons is reduced. Accordingly, while a pMOS transistor having an improved low voltage can be obtained, the performance of an nMOS transistor cannot be improved, with a result that the performance of the CMOS cannot be significantly improved.
As described above, according to the related art method, it has been impossible to obtain a high performance CMOS and hence to produce a semiconductor device having a high performance and a low power consumption.
An object of the present invention is to provide a semiconductor device capable of increasing the operational speed and reducing the power consumption by providing an nMOS in which the mobility of electrons is increased by a strain effect and a pMOS in which the mobility of positive holes is increased by the strain effect on a common base-substrate, and to provide a method of fabricating the semiconductor device by using the same fabrication process as that used for fabricating a related art CMOS in which the base-substrate is configured as only a silicon substrate.
To achieve the above object, according to a first aspect of the present invention, there is provided a semiconductor device including an n-channel field effect transistor and a p-channel field effect transistor, the both transistors being provided on a common base-substrate, wherein a surface region, in which the n-channel field effect transistor is provided, of the base-substrate includes: a silicon substrate; a buffer layer formed on the silicon substrate, the buffer layer being made from a silicon-germanium compound having a germanium concentration gradually increased toward an upper surface of the buffer layer; a relax layer formed on the buffer layer, the relax layer being made from a silicon-germanium compound having a germanium concentration nearly equal to that of a surface portion of the buffer layer; and a silicon layer formed on the relax layer, and wherein a surface region, on which the p-channel field effect transistor is provided, of the base-substrate, includes: the silicon substrate; a silicon-germanium compound layer formed on the silicon substrate; and a cap layer formed on the silicon-germanium compound layer, the cap layer being made from silicon. In the above-mentioned semiconductor device, source/drain regions of the n-channel field effect transistor may be formed in the silicon layer, and the regions of the p-channel field effect transistor may be formed in the silicon-germanium compound layer.
With this configuration, since the semiconductor device has the CMOS configuration in which the n-channel field effect transistor and the p-channel field effect transistor are provided on the common base-substrate, the power consumption can be reduced. Further, in the n-channel field effect transistor, since the silicon layer is provided on the relax layer made from the silicon-germanium compound whose stress is relaxed because it is formed on the buffer layer, tensile stress is generated in the silicon layer, so that the mobility of electrons is increased by the strain effect due to tensile stress in the silicon layer; and in the p-channel field effect transistor, since the silicon-germanium compound layer is provided on the silicon substrate, compressive stress is generated in the silicon-germanium compound layer, so that the mobility of positive holes is increased due to the strain effect due to the compressive stress in the silicon-germanium compound layer. According to the semiconductor device of the present invention, since the source/drain regions are formed in each of the silicon layer and silicon-germanium compound layer having the above-described unique properties, the operational speeds of the n-channel field effect transistor and p-channel field transistor can be improved.
According to a second aspect of the present invention, there is provided a method of fabricating a semiconductor device in which an n-channel field effect transistor and a p-channel field effect transistor are provided on a common base-substrate, the method including the steps of: etching a surface layer of an n-channel region, in which the n-channel field effect transistor is to be formed, of a silicon substrate, to form a stepped recess at the n-type region; forming a buffer layer made from a silicon-germanium compound having a germanium concentration gradually increased toward an upper surface of the buffer layer on the silicon substrate; forming a relax layer made from a silicon-germanium compound having a germanium concentration nearly equal to that of a surface portion of the buffer layer on the buffer layer; forming a silicon layer on the relax layer; removing the silicon layer, the relax layer, and the buffer layer in a p-type region, on which a p-channel field effect transistor is to be formed, of the silicon substrate, by etching using a resist pattern as a mask; forming a silicon-germanium compound layer on both the silicon substrate and the silicon layer; planarizing the surface of the silicon-germanium compound layer in a state that the silicon layer is exposed in the n-type region and the silicon-germanium compound layer is left in the p-type region; forming a silicon epitaxial layer on both the silicon layer and the silicon-germanium compound layer, to form a silicon layer composed of the silicon layer and the silicon epitaxial layer in the n-type region, and to form a cap layer composed of the silicon epitaxial layer in the p-type region; and forming gate electrodes on the silicon layer in the n-type region and on the cap layer in the p-type region via a gate insulating film, and forming n-type source/drain regions in the silicon layer and p-type source/drain regions in the silicon-germanium compound layer.
With this configuration, the n-channel field effect transistor, in which the silicon layer is formed on the silicon substrate via the buffer layer and relax layer and the source/drain regions are formed in the silicon layer, is provided in the n-type region; and a p-channel field effect transistor, in which a silicon-germanium compound layer is formed on the silicon substrate and the source/drain regions are formed in the silicon-germanium compound layer, is provided in the p-type region. In this case, the silicon-germanium layer is formed in the state that the buffer layer, relax layer, and silicon layer are left in the stepped recess formed at the n-type region of the silicon substrate, and the surface of the silicon-germanium compound layer is planarized by a CMP process in such a manner as to expose the silicon layer only in the n-type region, and accordingly, the gate electrodes of the n-channel field effect transistor and p-channel field effect transistor are formed on a planar base-substrate. As a result, the planar structure of the semiconductor device of the present invention becomes similar to that of a related art semiconductor device in which the base-substrate is configured as only a silicon substrate.